Plasma display panels (hereinafter referred to as PDPs) have come to attention as thin, high-resolution display devices in recent years. A PDP has a number of discharge cells formed by data electrodes and sustain and scan electrodes that are arranged in a matrix. The discharge of a discharge cell is controlled by a data-electrode line and a scan-electrode and sustain-electrode lines which cross the data-electrode line at right angles. A desired image is displayed by turning on and off the discharge light emission of the discharge cells.
To drive such a PDP, semiconductor circuit devices are used which include a level shifter converting digital RGB color image signal into a high voltage capable of driving the PDP.
Such a conventional semiconductor circuit device will be described with reference to drawings.
FIG. 10 is a schematic diagram of a typical plasma display panel; FIG. 11 is a block diagram of a conventional data-line driver for driving a PDP; FIG. 12 is a schematic circuit diagram of a conventional driving circuit; FIG. 13 is a driving waveform chart of the conventional driving circuit; FIG. 14A is a schematic diagram showing a structure of a conventional PDP-driving circuit; FIG. 14B is a schematic cross-section diagram of the conventional PDP-driving circuit, showing the cross-section taken along line A-B in FIG. 14A; and FIG. 15 is a current characteristic diagram of an NPN parasitic bipolar transistor in the conventional driving circuit.
As shown in FIG. 10, the display panel (PDP) 900 is driven by multiple scan-line drivers 902 connected to multiple scan-electrode lines 901 and multiple display-data-line drivers 904 connected to multiple display-data-electrode lines 903. In the PDP that provides color display, each display-data-electrode line has three color electrodes using phosphors of three different colors, R (red), G (green), and B (blue), and the display-data-electrode lines are driven individually to achieve color display.
Image data inputted through a data input terminal is serially provided to a shift register 905, as shown in FIG. 11. The serial data received by the shift register 905 is converted into parallel data by the shift register 905 and then held in a latch circuit 906. The parallel data held in the latch circuit 906 undergoes voltage transduction in a level shifting circuit 907 and the level-shifted data is outputted selectively from driving output terminals O1-Om through a driving circuit 908 as a ground potential (GND) or a power-supply potential (VCC) and is applied to the display-data electrodes 903.
FIG. 12 shows a portion of the driving circuit 908, which is formed as a multi-output driver in which a number of push-pull circuits are provided adjacently. Here, an output terminal On and another output terminal On+1 are adjacent driving output terminals and a driving-power-supply terminal 103 and a ground terminal 130 are provided for each of the output terminals On and On+1. In the configuration in which multiple driving output terminals are provided adjacently in this way, superimposed on an output from an output terminal is a self-noise associated with a change in an output from an output driving terminal adjacent to the terminal or an external noise from the panel, as shown in FIG. 13.
A high-density N-diffusion layer 106 and an adjacent high-density N-diffusion layer 160 of a transistor that implement an output buffer are formed on a P-well 108 the potential of which is fixed to the ground potential (GND). Thus, an NPN parasitic bipolar transistor 102 is formed between an output terminal OUTn 104 and its adjacent output terminal OUTn+1 105, in the path from the high-density N-diffusion layer 106 coupled to the output terminal OUTn 104, the P-well 108 coupled to the GND, to the N-diffusion layer 160 coupled to the output terminal OUTn+1 105.
If self-noise or external noise generates a potential difference greater than or equal to the built-in voltage between the N-diffusion layer 160 coupled to the output terminal OUTn+1 105 and the P-well 108 while the output terminal OUTn 104 is in the “power-supply potential (VCC)” output state and the output terminal OUTn+1 105 is in the “ground potential (GND)” output state, the NPN parasitic bipolar transistor formed between the adjacent output terminals turns on.
As a result, an emitter current Ie flows from the P-well 108 to OUTn+1 105 (the N-diffusion layer coupled to this terminal is hereinafter referred to as the emitter) and a base current Ib flows from the ground terminal 130 to the P-well 108, which causes a collector current Ic to flow from the output terminal OUTn 104 (the N-diffusion layer coupled to this terminal is hereinafter referred to as the collector) to the P-well 108 (herein after referred to as the base). If the collector current Ic flowing through the collector which is biased to a high potential exceeds a permissible current value limit, thermal destruction of the collector is caused, which results in a malfunction.
The current characteristics of an NPN parasitic bipolar transistor are determined by a physical design, diffusion density, and the voltage between the collector and the emitter, as shown in FIG. 15; the higher the driving-power-supply voltage (VCC) or the greater the collector current, the higher the electric field applied to the junction region of the collector and therefore the more likely it is that thermal destruction will occur. On the other hand, because the collector voltage is determined by the panel driving voltage, the tolerance against malfunctions and destruction can be improved by minimizing the collector current without lowering the driving-power-supply voltage.
To address the above-described problem, other driving circuits provide a sufficient distance between adjacent transistors or use an SOI (Silicon Oxide Insulated) process that insulates transistors with a silicon oxide film.